The present application relates to methods and apparatus for controlling transistors. The application further relates to but is not limited to methods of apparatus for controlling voltage swing variation in open drain transmitters.
Typical open drain transmitter architectures generate an accurate voltage swing using a defined tail current of a differentially coupled pair of transmitters. FIG. 1 shows an example of a typical open drain transmitter architecture. A typical open drain transmitter comprises open drain transmitter circuitry comprising a first and second N-channel transistor 122 and 123 which receives a data and a complement data input at their respective gates. A respective source for the first 122 and second 123 N-channel transistor is coupled to a drain connection of a third N-channel transistor 121. The third N-channel transistor 121 has a source connection coupled to ground. The third N-channel transistor 121 sets the current through the first and second N-channel transistors 122 and 123 forming driving transistors.
A respective drain connection of the first and second N-channel transistors 122 and 123 is coupled to a respective source connection of a fifth and sixth transistor 124 and 125 respectively. A respective gate connection of the fourth and fifth transistor 124 and 125 is coupled to a signal Vbias received from bias circuitry 110. A drain connection of the fourth transistor 124 is coupled to an output pad B 126 and a drain connection of the fifth transistor 125 is coupled to an output pad A 127. The output pad B and A 126 and 127 are respectively coupled to a first and second terminating resistor 131 and 132 which are coupled in series to a terminating voltage 133. The external resistors 131 and 132 and terminating voltage 133 form part of a receiver 130.
A gate connection of the third transistor 121 is coupled to a gate connection of a sixth transistor 111 which is part of biasing circuitry 110. A source of the sixth transistor 111 is coupled to ground and a drain connection of the sixth transistor 111 is coupled to a source connection of a seventh transistor 112 as well as to the gate connection of the sixth transistor 111. The seventh transistor 112 gate connection is coupled to a voltage VDD while the drain of the seventh transistor 112 is coupled to the source of an eighth transistor 114. A gate voltage of the eighth transistor 114 provides the Vbias signal to the fourth and fifth transistors 124 and 125 and is further coupled to a drain connection of the eighth transistor 114. The drain connection of the eighth transistor 114 is also coupled to a current source 116 which in turn is coupled to the voltage source VDD 115.
The first and second transistors 122 and 123 form a differential transistor pair which receives differential data at their respective gates. The current through these transistors is set by the third transistor 121 which forms a current mirror with the sixth transistor 111. The sixth transistor 111 and seventh transistor 112 set the current through the biasing circuitry 110 and determine the current provided by current source 116. This current in turn biases the eighth transistor 114 which provides a suitable bias voltage at the gates of the fourth and fifth transistors 124 and 125. The fourth and fifth transistors 124 and 125 are cascode transistors that are implemented to protect the driving transistors by preventing their exposure to a high termination voltage.
In a typical open drain transmitter architecture, the driver transistors 122 and 123 do not receive the full circuit voltage VDD as their gate source voltage. The driver transistors 122 and 123 are typically in a linear region and therefore their size must increase in order to provide the required voltage drop at pad B and pad A. This in turn slows down the switching operation of the circuit.
It has been proposed to remove the tail current source of current mirror transistors 111 and 121 in order to provide the full voltage drop of VDD across the gate source of the driver transistors. This results in the current through the driver transistors being controlled by the cascode transistors 124 and 125. This circuit attempts to have the drive current of the cascode transistors 124 and 125 equal to the drive current of the eighth transistor 114. However a difference between the drain source voltage VDS of the eighth transistor 114 and the VDS of the cascode transistors 124 and 125 may lead to a current mismatch due to a λVDS factor. Additionally, the drain voltage of the eighth transistor 114 is highly dependent on process variations in the source voltage.
It has further been proposed to implement additional cascode transistors as an additional level between the cascode transistors 124 and 125 and pads A and B 126 and 127. This however may slow down the transmitter considerably and impact on the headroom of the circuit. Alternatively an operational amplifier may be used to implement an effective equalization of the drain voltages of the cascode transistors and biasing transistor 114. This design however is not a power/area optimized design and additionally requires an operational amplifier and additional circuitry for the operational amplifier compensation.
What is desired is embodiments of the invention that attempt to address the above limitations.